3A001 Category 3A

Electronic items as follows (see List of Items Controlled).

Category 3: Electronics

Reasons for control

• NS: National security
• RS: Regional stability
• MT: Missile technology
• NP: Nuclear nonproliferation
• AT: Anti-terrorism

List-based license exceptions

Items

1. a. General purpose integrated circuits, as follows:
2. a.1. Integrated circuits designed or rated as radiation hardened to withstand any of the following:
3. a.1.a. A total dose of 5 × 10 3 Gy (Si), or higher;
4. a.1.b. A dose rate upset of 5 × 10 6 Gy (Si)/s, or higher; or
5. a.1.c. A fluence (integrated flux) of neutrons (1 MeV equivalent) of 5 × 10 13 n/cm 2 or higher on silicon, or its equivalent for other materials;
6. a.2. “Microprocessor microcircuits,” “microcomputer microcircuits,” microcontroller microcircuits, storage integrated circuits manufactured from a compound semiconductor, analog-to-digital converters, integrated circuits that contain analog-to-digital converters and store or process the digitized data, digital-to-analog converters, electro-optical or “optical integrated circuits” designed for “signal processing”, field programmable logic devices, custom integrated circuits for which either the function is unknown or the control status of the equipment in which the integrated circuit will be used in unknown, Fast Fourier Transform (FFT) processors, Static Random-Access Memories (SRAMs), or 'non-volatile memories,' having any of the following:
7. a.2.a. Rated for operation at an ambient temperature above 398 K (+125 °C);
8. a.2.b. Rated for operation at an ambient temperature below 218 K (−55 °C); or
9. a.2.c. Rated for operation over the entire ambient temperature range from 218 K (−55 °C) to 398 K (+125 °C);
10. a.3. “Microprocessor microcircuits”, “microcomputer microcircuits” and microcontroller microcircuits, manufactured from a compound semiconductor and operating at a clock frequency exceeding 40 MHz;
11. a.4. [Reserved]
12. a.5. Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) integrated circuits, as follows:
13. a.5.a. ADCs having any of the following:
14. a.5.a.1. A resolution of 8 bit or more, but less than 10 bit, with a “sample rate” greater than 1.3 Giga Samples Per Second (GSPS);
15. a.5.a.2. A resolution of 10 bit or more, but less than 12 bit, with a “sample rate” greater than 600 Mega Samples Per Second (MSPS);
16. a.5.a.3. A resolution of 12 bit or more, but less than 14 bit, with a “sample rate” greater than 400 MSPS;
17. a.5.a.4. A resolution of 14 bit or more, but less than 16 bit, with a “sample rate” greater than 250 MSPS; or
18. a.5.a.5. A resolution of 16 bit or more with a “sample rate” greater than 65 MSPS;
19. a.5.b. Digital-to-Analog Converters (DAC) having any of the following:
20. a.5.b.1. A resolution of 10-bit or more but less than 12-bit, with an 'adjusted update rate' of exceeding 3,500 MSPS; or
21. a.5.b.2. A resolution of 12-bit or more and having any of the following:
22. a.5.b.2.a. An 'adjusted update rate' exceeding 1,250 MSPS but not exceeding 3,500 MSPS, and having any of the following:
23. a.5.b.2.a.1. A settling time less than 9 ns to arrive at or within 0.024% of full scale from a full scale step; or
24. a.5.b.2.a.2. A 'Spurious Free Dynamic Range' (SFDR) greater than 68 dBc (carrier) when synthesizing a full scale analog signal of 100 MHz or the highest full scale analog signal frequency specified below 100 MHz; or
25. a.5.b.2.b. An 'adjusted update rate' exceeding 3,500 MSPS;
26. a.6. Electro-optical and “optical integrated circuits”, designed for “signal processing” and having all of the following:
27. a.6.a. One or more than one internal “laser” diode;
28. a.6.b. One or more than one internal light detecting element; and
29. a.6.c. Optical waveguides;
30. a.7. 'Field programmable logic devices' having any of the following:
31. a.7.a. A maximum number of single-ended digital input/outputs of greater than 700; or
32. a.7.b. An 'aggregate one-way peak serial transceiver data rate' of 500 Gb/s or greater;
33. a.8. [Reserved]
34. a.9. [Reserved]
35. a.10. Custom integrated circuits for which the function is unknown, or the control status of the equipment in which the integrated circuits will be used is unknown to the manufacturer, having any of the following:
36. a.10.a. More than 1,500 terminals;
37. a.10.b. A typical “basic gate propagation delay time” of less than 0.02 ns; or
38. a.10.c. An operating frequency exceeding 3 GHz;
39. a.11. Digital integrated circuits, other than those described in 3A001.a.3 to 3A001.a.10 and 3A001.a.12, based upon any compound semiconductor and having any of the following:
40. a.11.a. An equivalent gate count of more than 3,000 (2 input gates); or
41. a.11.b. A toggle frequency exceeding 1.2 GHz;
42. a.12. Fast Fourier Transform (FFT) processors having a rated execution time for an N-point complex FFT of less than (N log2 N)/20,480 ms, where N is the number of points;
43. a.13. Direct Digital Synthesizer (DDS) integrated circuits having any of the following:
44. a.13.a. A Digital-to-Analog Converter (DAC) clock frequency of 3.5 GHz or more and a DAC resolution of 10 bit or more, but less than 12 bit; or
45. a.13.b. A DAC clock frequency of 1.25 GHz or more and a DAC resolution of 12 bit or more;
46. a.14. Integrated circuits that perform or are programmable to perform all of the following:
47. a.14.a. Analog-to-digital conversions meeting any of the following:
48. a.14.a.1. A resolution of 8 bit or more, but less than 10 bit, with a “sample rate” greater than 1.3 Giga Samples Per Second (GSPS);
49. a.14.a.2. A resolution of 10 bit or more, but less than 12 bit, with a “sample rate” greater than 1.0 GSPS;
50. a.14.a.3. A resolution of 12 bit or more, but less than 14 bit, with a “sample rate” greater than 1.0 GSPS;
51. a.14.a.4. A resolution of 14 bit or more, but less than 16 bit, with a “sample rate” greater than 400 Mega Samples Per Second (MSPS); or
52. a.14.a.5. A resolution of 16 bit or more with a “sample rate” greater than 180 MSPS; and
53. a.14.b. Any of the following:
54. a.14.b.1. Storage of digitized data; or
55. a.14.b.2. Processing of digitized data;
56. b. Microwave or millimeter wave items, as follows:
57. b.1. “Vacuum electronic devices” and cathodes, as follows:
58. b.1.a. Traveling-wave “vacuum electronic devices,” pulsed or continuous wave, as follows:
59. b.1.a.1. Devices operating at frequencies exceeding 31.8 GHz;
60. b.1.a.2. Devices having a cathode heater with a turn on time to rated RF power of less than 3 seconds;

Related controls

(1) See Category XV of the USML for certain “space-qualified” electronics and Category XI of the USML for certain ASICs, 'transmit/receive modules,' 'transmit modules,' or 'MMICs' “subject to the ITAR.” (2) See also 3A090, 3A101, 3A201, 3A611, 3A901 for cryogenic CMOS integrated circuits and parametric signal amplifiers or quantum limited amplifiers not controlled by 3A001, 3A991, and 9A515.

Notes

Note: See § 740.2(a)(9)(ii) of the EAR for license exception restrictions for ECCN 3A001.z.

Note 1: Integrated circuits include the following types:: “Monolithic integrated circuits”;: “Hybrid integrated circuits”;: “Multichip integrated circuits”;: “Film type integrated circuits”, including silicon-on-sapphire integrated circuits;: “Optical integrated circuits”;: “Three dimensional integrated circuits”;: “Monolithic Microwave Integrated Circuits” (“MMICs”).

Note: 3A001.a.1.c does not apply to Metal Insulator Semiconductors (MIS).

Technical Note: For the purposes of 3A001.a.2, 'non-volatile memories' are memories with data retention over a period of time after a power shutdown.

N.B.: For cryogenic CMOS integrated circuits not specified by 3A001.a.2, see 3A901.a.

Note: 3A001.a.2 does not apply to integrated circuits designed for civil automobile or railway train applications.

Note: 3A001.a.3 includes digital signal processors, digital array processors and digital coprocessors.

N.B.: For integrated circuits that contain analog-to-digital converters and store or process the digitized data see 3A001.a.14.

Technical Notes: For the purposes of 3A001.a.5.a: 1. A resolution of n bit corresponds to a quantization of 2 n levels. 2. The resolution of the ADC is the number of bits of the digital output that represents the measured analog input. Effective Number of Bits (ENOB) is not used to determine the resolution of the ADC. 3. For “multiple channel ADCs”, the “sample rate” is not aggregated and the “sample rate” is the maximum rate of any single channel. 4. For “interleaved ADCs” or for “multiple channel ADCs” that are specified to have an interleaved mode of operation, the “sample rates” are aggregated and the “sample rate” is the maximum combined total rate of all of the interleaved channels.

Technical Notes: For the purposes of 3A001.a.5.b: 1. 'Spurious Free Dynamic Range' (SFDR) is defined as the ratio of the RMS value of the carrier frequency (maximum signal component) at the input of the DAC to the RMS value of the next largest noise or harmonic distortion component at its output. 2. SFDR is determined directly from the specification table or from the characterization plots of SFDR versus frequency. 3. A signal is defined to be full scale when its amplitude is greater than −3 dBfs (full scale). 4. 'Adjusted update rate' for DACs is: a. For conventional (non-interpolating) DACs, the 'adjusted update rate' is the rate at which the digital signal is converted to an analog signal and the output analog values are changed by the DAC. For DACs where the interpolation mode may be bypassed (interpolation factor of one), the DAC should be considered as a conventional (non-interpolating) DAC. b. For interpolating DACs (oversampling DACs), the 'adjusted update rate' is defined as the DAC update rate divided by the smallest interpolating factor. For interpolating DACs, the 'adjusted update rate' may be referred to by different terms including: • input data rate • input word rate • input sample rate • maximum total input bus rate • maximum DAC clock rate for DAC clock input

Note: 3A001.a.7 includes:: Complex Programmable Logic Devices (CPLDs);: Field Programmable Gate Arrays (FPGAs);: Field Programmable Logic Arrays (FPLAs);: Field Programmable Interconnects (FPICs).

N.B.: For integrated circuits having field programmable logic devices that are combined with an analog-to-digital converter, see 3A001.a.14.

Technical Notes: For the purposes of 3A001.a.7: 1. Maximum number of digital input/outputs in 3A001.a.7.a is also referred to as maximum user input/outputs or maximum available input/outputs, whether the integrated circuit is packaged or bare die. 2. 'Aggregate one-way peak serial transceiver data rate' is the product of the peak serial one-way transceiver data rate times the number of transceivers on the FPGA.

Technical Note: For the purposes of 3A001.a.12, when N is equal to 1,024 points, the formula in 3A001.a.12 gives an execution time of 500 µs.

Technical Note: For the purposes of 3A001.a.13, the DAC clock frequency may be specified as the master clock frequency or the input clock frequency.

N.B.: 1: For analog-to-digital converter integrated circuits see 3A001.a.5.a.

N.B.: 2: For field programmable logic devices see 3A001.a.7.

Technical Notes: For the purposes of 3A001.a.14: 1. A resolution of n bit corresponds to a quantization of 2 n levels. 2. The resolution of the ADC is the number of bits of the digital output of the ADC that represents the measured analog input. Effective Number of Bits (ENOB) is not used to determine the resolution of the ADC. 3. For integrated circuits with non- interleaving “multiple channel ADCs”, the “sample rate” is not aggregated and the “sample rate” is the maximum rate of any single channel. 4. For integrated circuits with “interleaved ADCs” or with “multiple channel ADCs” that are specified to have an interleaved mode of operation, the “sample rates” are aggregated and the “sample rate” is the maximum combined total rate of all of the interleaved channels.

Technical Note: For the purposes of 3A001.b, the parameter peak saturated power output may also be referred to on product data sheets as output power, saturated power output, maximum power output, peak power output, or peak envelope power output.

N.B.: For parametric signal amplifiers or Quantum-limited amplifiers (QLAs) not specified by 3A001.b, see ECCN 3A901.b.

Note 1: 3A001.b.1 does not control “vacuum electronic devices” designed or rated for operation in any frequency band and having all of the following: a. Does not exceed 31.8 GHz; and b. Is “allocated by the ITU” for radio-communications services, but not for radio-determination.

Note 2: 3A001.b.1 does not control non-“space-qualified” “vacuum electronic devices” having all the following: a. An average output power equal to or less than 50 W; and b. Designed or rated for operation in any frequency band and having all of the following: 1. Exceeds 31.8 GHz but does not exceed 43.5 GHz; and 2. Is “allocated by the ITU” for radio-communications services, but not for radio-determination.

Technical Note: For the purposes of 3A001.b.1.d, 'dual mode' means the “vacuum electronic device” beam current can be intentionally changed between continuous-wave and pulsed mode operation by use of a grid and produces a peak pulse output power greater than the continuous-wave output power.

N.B.: For “MMIC” amplifiers that have an integrated phase shifter see 3A001.b.12.

Note 1: [Reserved]

Source: eCFR, version 2026-08-01, retrieved 2026-08-20T04:04:59+00:00.